考量電壓島佈局環境之X架構時脈繞線

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Title:	考量電壓島佈局環境之X架構時脈繞線
Other Titles:	The X-Architecture Clock Routing With Considering Voltage-Island Placement
Authors:	尤志豪 Yu, Chin-hao
Contributors:	資訊管理學系碩士班蔡加春 Chia-chun Tsai
Keywords:	X繞線;功率消耗;多重電壓佈局;零時脈差異;電壓島 multi-voltage placement;zero-skew;voltage island;X-routing;power consumption
Date:	2009
Issue Date:	2015-03-25 15:25:02 (UTC+8)
Abstract:	時脈繞線(clock routing)在VLSI設計系統中，延遲時間、總繞線長度及功率消耗是影響系統效能甚巨的三個因素，而不同的繞線方法除了影響到繞線長度，相對地也會影響延遲時間的增減和功率消耗，這些都是在積體電路的繞線技術中需要被關注的問題。　　　其次，由延遲時間引申而來的時脈差異(clock skew)也是我們關心的問題，過於嚴重的時脈差異所引起的訊號時間差，同樣的對系統效能也會產生負面影響，所以在理想的VLSI設計目標上，我們通常希望可以達到所謂的零時脈差異(zero-skew)，亦被稱為零時脈差異時脈樹(zero-skew clock tree)。　　　目前的VLSI設計環境中，電壓島的佈局環境已非常普及，且多電壓島的考量更可節省功率的消耗量，因此，在多電壓島的佈局環境下，不得不重視時脈繞線的問題。本篇論文的主要研究即是基於這樣的考量，使用一種稱為DME-X的時脈繞線法及兼具有翻轉(flip)考量的DME-XP演算法，即結合X結構與DME演算法，應用在不同區塊配置不同電壓源的多電壓島佈局環境中，完成零時脈差異X結構時脈樹，以降低延遲時間、繞線長度、穿孔數及功率消耗等因素；並比較不同的佈局環境條件下，進一步解析這些因素的變化性。　　　根據我們提出的DME-XP時脈繞線方法應用在IBM之五個標準例子，將每個例子分割為二至三個電壓島佈局情況下，與原始單電壓島之實驗結果做比較。在雙電壓島的情況下，其延遲時間平均增加了12.8%，繞線長度僅增加了0.3%，穿孔數則是減少0.74%，而功率消耗則是降低了14%；在三電壓島的情況下，其延遲時間平均減少了27.1%，繞線長度僅增加了0.3%，穿孔數則僅增加0.24%，但功率消耗更是降低了25%。從這些比較結果，顯示我們的時脈繞線方法對多重電壓島佈局環境是有效的，尤其是在降低功率消耗方面。　Considering the clock routing in a VLSI design system, clock delay, total wire length, and power consumption are three essential factors to impact the system performance. Different routing methods result the various total wire lengths and also make some influences to the clock delay and power consumption. These are needed to pay attention in the VLSI routing techniques. 　　Clock skew is another important factor which is caused from different clock delays. An enough large clock skew can make very negative effects for the system performance. Therefore, the ideal objective of clock routing is that we expect to obtain an exact zero-skew clock tree to a VLSI system.　　In the recent VLSI design environment, the voltage-island placement is most one of universal methodologies to save the power consumption in physical design. So, we cannot ignore the clock routing problem in the voltage-island placement environment. The main structure in this thesis is to solve the above clock routing problem in the voltage-island placement by using DME-XP routing method which is considering the post refinement of an extra flip. These methods are based on X-architecture and DME algorithm to make X-clock routing which can reduce total wire length and clock delay. Moreover, we apply the above X-clock routing in a multiple voltage-island placement to construct a zero-skew X-architecture clock tree. Then, we observe the effects in terms of clock delay, wire length, via cost, and power consumption from the results at different placements.　　The proposed approach of DME-XP has applied to the IBM five benchmarks, which are partitioned into two- and three-voltage-island placements. According to our experiments, we compare their results with that of original placement using the same DME-XP clock routing. For the cases of two-voltage island, the clock delay and total wire length increase 12.8% and 0.3% on average, respectively; however, the via cost and power consumption reduce 0.74% and 14.2% on average, respectively. For the cases of three-voltage islands, the total wire length and via cost increase 0.3% and 0.24% on average, respectively; however, the clock delay and power consumption decrease up to 27.1% and 14.2% on average, respectively. From above comparisons, our X-clock routing approach is effective for a multi-voltage island placement, especially in the reduction of power consumption.
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