自從超大型積體電路的製程技術進入深次微米之後，影響系統效能的因素已經由原先的閘級延遲改變為連線延遲，因此如何減少連線延遲便成為提昇系統效能的一個重要目標。以往對於連線延遲的計算方式是採用RC或者RLC模型，但隨著晶片的工作頻率不斷提昇，使得原本不被考慮的電感效應越來越明顯。在本論文中則使用與HSPICE誤差值極小的fitted Elmore delay(FED)模型用來評估與計算連線延遲。 匯流排普遍存在於一顆晶片內，其連線延遲也直接影響晶片內部電路的執行效能，如何減少匯流排上的訊號延遲將是影響電路執行效能的關鍵因素。本論文提出三個演算法來降低多源多汲(multi-source multi-sink)匯流排上的訊號延遲，此演算法是以FED 模型來計算連線延遲，我們在匯流排上找出臨界路徑上每一個線段後，平均插入適當的雙向訊號重複器同時調整其大小，並繼續找出臨界路徑中訊號重複器插入的最佳位置來改善連線延遲，反覆此程序，直到臨界路徑的連線延遲不能再改善為止。根據實驗結果顯示，我們所提出的演算法與文獻比較對於不同製程參數0.18微米和0.13微米的連線延遲至少可以改善1.8%和3.7%。 Since the advance of deep submicron meter technology in VLSI, the performance dominating factor is changed from gate delay to interconnect delay. Therefore, how to reduce interconnection delay becomes a critical goal for improving system performance. The RC and RLC delay models are two widely used models for calculating the interconnection delay in the past. But the increment of working frequency of chip leads the designer to re-exam the effect of inductance. In this thesis the fitted Elmore delay (FED) model which has less simulation error compared to HSPICE is used for computing and evaluating interconnection delay. Bus is an important transmission media inside a chip and its wire connection also significantly influences the performance of circuit. Eliminating the propagation delay of signal on the bus helps us to increase the performance of circuit. In this thesis we also proposed a greedy algorithm to reduce the signal transmission delay for multi-source and multi-sink structures on the bus. In our proposed algorithm, the bidirectional repeaters are averagely inserted into the critical path and the size of repeaters is also adjusted. Afterward, the best position where the repeater should be inserted is found to improve the delay. The above steps are repeatedly executed until the minimum delay is stable. Experimental results show that our proposed algorithm can at least reduce 1.8% and 3.7% propagation delay time for the processes of 0.18μm and 0.13μm, respectively, while compared to the literatures respectively.
