三維疊接SoC為多層次(multi-layer)的積體電路，每層次包含數個不同功能區塊模組所組合起來，具有區域性的控制、位址、資料等三種主要匯流排而將這些模組連結形成區域系統匯流排，各層次 (layer)將這三種區域匯流排以適量貫穿矽層穿孔(TSVs)相互連結起來而成為整顆SoC的全域系統匯流排(system buses)，其中在全域的資料匯流排之資訊存取時間快慢，最直接影響3D疊接SoC的系統執行效能。 資料匯流排之資訊存取時間最小化的一般方法，以動態橋接分段匯流排或跨越匯流排(Dynamic bridge segmented or by-pass bus)可有效的提高資訊存取速度；在資料匯流排中插入適當大小的緩衝器或重複器(sized buffers or repeaters)，亦可有效地降低資訊存取時間或資料傳播延遲時間。而在3D全域資料匯流排之資訊存取時間精簡化，牽涉到驅動各層次之TSVs個數的負載量及各區域資料匯流排之連線總電阻與總電容的負載量，以動態橋接分段匯流排或跨越匯流排的方法及在資料匯流排中插入適當大小的緩衝器或重複器(sized buffers or repeaters)等皆可整合適用，達到有效的提高全域資料存取速度或降低全域資訊傳播延遲時間。本研究計畫首先針對多層次3D疊接SoC在不同的時序下，資料在全域資料匯流排之資訊存取時間或傳播延遲時間之最小化的問題定義如下：輸入為已知有多個層次(Multi-layer)以TSVs疊接組成一個3D系統晶片，每個層次(layer)含有數個IP模組且都有自己的區域資料匯流排(local data bus)，並以TSV將每個層次的區域資料匯流排(local data bus)疊接成為全域匯流排(global data bus);已知有p 個時序，每個時序可將信號從一個源頭端(source terminal)經由區域資料匯流排或全域匯流排同時傳送到多個汲極端(sink terminals)。輸出為依照每個時序之信號從一個source端經由區域資料匯流排或全域匯流排同時傳送到多個sink端，決定插入適當雙向傳輸閘(Transmission gates)或匯流排開關(bus switches)來阻隔非必要的匯流排負載電容量及插入雙向可調整大小的重複器(repeater)來提升信號存取 時間，使得其全域最大的信號存取時間為最小化，且目標為Min(Max(Delay；.))，i為source端，_/為sink 端。本研究計畫接著對以上問題提出一個三維資料匯流排傳輸效能驅動，並建置於傳輸閘隔離開關與插入重複器及調整其大小，對最大的臨界傳播延遲時間做最小化之演算法，已知n為三維疊接SoC全域資料匯流排傳輸可被插入重複器位置的線段數目，p為三維疊接SoC全域資料匯流排傳輸的時序數目，在所有的時序下之資料傳輸，每次找到最大的臨界傳播延遲時間及其傳輸路徑，此時當然考量隔離那些不動作匯流排的負載，並嘗試在此傳輸路徑之可被插入重複器位置的線段數目々，插入r„ (rn < k < n)個重複器，並依序調整其重複器大小，直到此大的臨界傳播延遲時間降至不能再降低為止。以上的動作一直重複到不能再改進為止，最後可得到最大的臨界傳播延遲時間之最小化結果，同時也可獲得哪些三維資料匯流排線段被插入不同大小之重複器，具體提升系統執行效能。 A 3D stacked SoC (System-on a Chip) is a multiple-layer integrated circuit. Each layer consists of a number of different function-based modules and has a local system buses that include the control bus, address bus, and data bus to connect these modules. A number of TSVs is used to vertically connect different local system buses located on each layer to form these local buses to be the global system buses of a 3D stacked SoC. It is noted that the data accessing time in global data bus is the key point for the system performance of a 3D stacked SoC. The general methods for minimizing the data accessing time in global data bus are still limited. One is to adopt the dynamic bridge segmented bus or by-pass bus that can effectively increase the data accessing speed. Another is to insert proper sized buffers or repeaters into the bus wire segments that can also effectively reduce the data propagation delay. Minimizing the data accessing time in the global data bus of 3D stacked SoC needs to consider the loading effects of TSVs and other local data buses. Integrating the above two solved methods is good idea for minimizing the propagation delay in the global data bus of 3D stacked SoC. The proposal first defines the above problem for minimizing the propagation delay in the global data bus in different periodic timings of 3D stacked SoC. The problem is defined and described as follows. Given a multi-layer 3D stacked SoC that has a number of TSVs to connect different local buses located on each layer. Given also a number of different periodic timings p, each periodic timing a signal is transmitted from a source to multiple sinks located on different local layers. The objective is to minimize the maximum propagation delay for all the periodic timings in global data bus by isolating the non-active local buses with transmission gates or bus switches and inserting the proper sized repeater. That is, Min(Max(De/a>^.))，i is source and j is sink. Then, the proposal proposes an algorithm for solving the above problem. n is the total number of bus segments in the global buses of a 3D stacked SoC and p is the total number of periodic timings. For the data transmission each periodic timing, we always find the maximal critical propagation delay and its transmitted critical path, meanwhile, isolating non-active local buses with bus switches is considered. We try to insert a number of rn (rn < k < n) repeaters into a number of k wire segments along the path and size them accordingly. This operation of adjusting repeaters’ size cannot stop until the maximal critical propagation delay is not improvement again. The above operation is repeated for all the different periodic timings until the maximal critical propagation delay cannot be reduced again. Finally, we can obtain the minimal maximal propagation delay with paying an small area of number of sized repeaters in the global buses of a 3D stacked SoC, as well as, the system performance is thus promoted.
